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? 2009-2013 microchip technology inc. ds80439m-page 1 dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 the dspic33fj06gs101/x02 and dspic33fj16gsx02/ x04 family devices that you have received conform functionally to the current device data sheet (ds70318 f ), except for the anomalies described in this document. the silicon issues discussed in the following pages are for silicon revisions with the device and revision ids listed in ta bl e 1 . the silicon issues are summarized in table 2 . the errata described in this document will be addressed in future revisions of the dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 silicon. data sheet clarifications and corrections start on page 17 , following the discussion of silicon issues. the silicon revision level can be identified using the current version of mplab ? ide and microchip?s programmers, debuggers and emulation tools, which are available at the microchip corporate web site ( www.microchip.com ). for example, to identify the silicon revision level using mplab ide in conjunction with a hardware debugger: 1. using the appropriate interface, connect the device to the hardware debugger. 2. open an mplab ide project. 3. configure the mplab ide project for the appropriate device and hardware debugger. 4. based on the version of mplab ide you are using, do one of the following: a) for mplab ide 8, select programmer > reconnect . b) for mplab x ide, select window > dashboard and click the refresh debug tool status icon ( ). 5. depending on the development tool used, the part number and device id and revision id values appear in the output window. the device and revision id values for the various dspic33fj06gs101/x02 and dspic33fj16gsx02/ x04 silicon revisions are shown in table 1 . note: this document summarizes all silicon errata issues from all revisions of silicon, previous as well as current. only the issues indicated in the last column of table 2 apply to the current silicon revision ( a4 ). note: if you are unable to extract the silicon revision level, please contact your local microchip sales office for assistance. table 1: silicon devrev values part number device id (1) revision id for silicon revision (2) a2 a3 a4 dspic33fj06gs101 0x0c00 0x3002 0x3003 0x3004 dspic33fj06gs102 0x0c01 dspic33fj06gs202 0x0c02 dspic33fj16gs402 0x0c04 dspic33fj16gs404 0x0c06 dspic33fj16gs502 0x0c03 dspic33fj16gs504 0x0c05 note 1: the device and revision ids (devid and devrev) are located at the last two implemented addresses in program memory. 2: refer to the ?dspic33f/pic24h flash programming specification? (ds70152) for detailed information on device and revision ids for your specific device. dspic33fj06gs101/x02 an d dspic33fj16gsx02/x04 family silicon errata and data sheet clarification
dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 ds80439m-page 2 ? 2009-2013 microchip technology inc. table 2: silicon issue summary module feature item number issue summary affected revisions (1) a2 a3 a4 pwm leading-edge blanking 1. reading lebconx registers, as well as writing individual bits and bytes within these registers, does not work. xxx pwm immediate updates 2. pwm immediate update mode (ieu = 1 ) for the master duty cycle register (mdc) is not functional. xxx pwm status bits 3. pwm fault status bits do not function if the associated pwm fault interrupts are disabled. xxx pwm clock 4. pwm output will exhibit jitter with some pwm clock divider settings. xxx pwm faults 5. if the pwm is in complementary, redundant and push- pull mode and the independent time base bit (itb) is set, the independent fault mode may not work as expected for the pwmxl pin. xxx pwm independent time base 6. the independent time base pwm outputs may not be synchronized with the master time base pwm outputs when both modes are used simultaneously. xxx pwm latched faults 7. in pwm latched fault mode, the pwm outputs may be latched on both the rising as well as the falling edge of the fault signal regardless of the fault input polarity selection (set with the fclconx bit setting). xxx pwm faults 8. a bit write to the clmod bit (bit 8) in the fclconx register, or consecutive writes to the lower byte and higher byte of the fclconx register, causes all other bits of the high byte to be loaded with zeros. xxx pwm sleep mode 9. the pwm module fails to wake the cpu from sleep mode on a pwm fault event. xxx comparator ? 10. for slow input signals, the comparator module may generate erroneous triggers/interrupts. xxx adc clock 11. selecting the primary frc (f vco ) as a clock source for the adc module by setting the slowclk bit (adcon<12>) to the default setting of ? 0 ?, does not work. xxx auxiliary clock module disable 12. when the pwmmd bit in the pmd1 register is set, the auxiliary clock to both the adc and pwm modules is disabled. xxx comparator interrupts 13. comparator interrupts are incorrectly generated when the high-speed analog comparator is configured for an inverted polarity setting (cmpconx = 1 ). xxx uart 4x mode 14. when the uart is in 4x mode (brgh = 1 ) and using two stop bits (stsel = 1 ), it may sample the first stop bit instead of the second one. xxx uart ir interface operations 15. the 16x baud clock signal on the bclk pin is present only when the module is transmitting. xxx i 2 c? 10-bit addressing mode 16. when the i 2 c? module is configured for 10-bit addressing using the same address bits (a10 and a9) as other i 2 c devices, the a10 and a9 bits may not work as expected. xxx pwm adc conversion 17. the pwm module may fail to trigger a conversion on certain adc pairs when the primary or secondary pwmx generator is selected as a trigger source. x note 1: only those issues indicated in the last column apply to the current silicon revision.
? 2009-2013 microchip technology inc. ds80439m-page 3 dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 pgec3/ pged3 programming pins device programming 18. when using the pgec3/pged3 pins for device programming, the programming time may be slower as compared to other available pgecx/pgedx pin pairs. xxx uart break character generation 19. the uart module will not generate back-to-back break characters. xxx pwm current limit 20. cycle-by-cycle current-limit operation does not work when the pwm module is configured for center-aligned mode. xxx pwm current reset mode 21. current reset mode does not work when the current-limit source (clsrc) occurs during, and persists past, the assertive time interval of the pwm, and leading-edge blanking time is less than the pwm assertive time interval. xxx uart irda ? encoder/ decoder and 8-bit operating mode 22. when the uart module is operating in 8-bit mode (pdsel = 0x ) and using the irda encoder/decoder (iren = 1 ), the module incorrectly transmits a data payload of 80h as 00h. xxx uart uxe interrupt 23. the uart error interrupt may not occur, or may occur at an incorrect time, if multiple errors occur during a short period of time. xxx i 2 c 10-bit addressing mode 24. when the i 2 c module is configured as a 10-bit slave with an address of 0x102, the i2cxrcv register content for the lower address byte is 0x01 rather than 0x02. xxx i 2 c 10-bit addressing mode 25. the 10-bit slave does not set the rbf flag or load the i2cxrcv register, on address match if the least significant bits (lsbs) of the address are the same as the 7-bit reserved addresses. xxx psv operations addressing modes 26. an address error trap occurs in certain addressing modes when accessing the first four bytes of any psv page. xxx comparator sleep mode 27. the comparator fails to wake the cpu from sleep mode when the internal voltage reference is used. xxx pwm independent time base 28. when updating the frequency on the fly, push-pull pwm outputs may not be synchronized with other pwm output modes. xxx analog comparator internal band gap reference voltage 29. the internal band gap reference voltage (intref) for the analog comparator does not meet the stated accuracy specifications. xxx auxiliary pll input frequency 30. for extended temperature devices, the auxiliary pll input frequency does not meet the published specification range. xxx adc current consumption in sleep mode 31. if the adc module is in an enabled state when the device enters sleep mode, the power-down current (i pd ) of the device may exceed the device data sheet specifications. xxx high-speed pwm pwm module enable 32. a glitch may be observed on the pwm pins when the pwm module is enabled after assignment of pin ownership to the pwm module. xxx reserved ? 33. ?? table 2: silicon issue summary (continued) module feature item number issue summary affected revisions (1) a2 a3 a4 note 1: only those issues indicated in the last column apply to the current silicon revision.
dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 ds80439m-page 4 ? 2009-2013 microchip technology inc. pwm duty cycle updates 34. when the pwm duty cycle update coincides with the pwm period rollover, the pwm output may be corrupted for one pwm period. xxx jtag active pull-up 35. in jtag mode, the tms pin will not have an active pull-up as required by the jtag specification. xxx spi framed master mode 36. when the spi module is configured in framed master mode and the frame sync pulse edge select bit (frmdly) is set to ? 1 ?, transmitting a word and then buffering another word in the spixbuf register before the transmission has completed, results in an incomplete transmission of the first data word. xxx comparator trigger voltage level 37. output signal transitions occurring on the dacout pin (with dac output disabled) can cause the comparator trigger voltage level to change. xxx cpu interrupt disable 38. when a previous disi instruction is active (i.e., the disicnt register is non-zero), and the value of the disicnt register is updated manually, the disicnt register freezes and disables interrupts permanently. xxx cpu div.sd 39. when using the div.sd instruction, the overflow bit is not getting set when an overflow occurs. xxx uart tx interrupt 40. a transmit (tx) interrupt may occur before the data transmission is complete. xxx jtag flash programming 41. jtag flash programming is not supported. x x x pwm edge-aligned complimentary mode 42. when operating in edge-aligned complimentary mode, the dead time could become 0. xxx pwm pwm module enable 43. if the pwm clock divider select register, ptcon2, is not equal to zero, the pwm module may or may not initialize from an override state xxx pwm pwm swap 44. if the pwm is configured for complimentary mode and the swap bit is enabled, the pwm outputs might operate as redundant mode when the phase value is greater than the programmed dead-time (dtrx) value. xxx pwm pwm in current-limit mode 45. a <8-ns glitch may be observed on the pwm output pins when the current-limit event occurs. xxx table 2: silicon issue summary (continued) module feature item number issue summary affected revisions (1) a2 a3 a4 note 1: only those issues indicated in the last column apply to the current silicon revision.
? 2009-2013 microchip technology inc. ds80439m-page 5 dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 silicon errata issues 1. module: pwm reading lebconx registers, as well as writing individual bits and bytes within these registers does not work. work around use a word write operation to modify lebconx registers. for example, to set the phr bit within the lebcon1 register, use the following c code: lebcon1 = 0x8000 there is no work around for reading lebconx registers. affected silicon revisions 2. module: pwm if pwm immediate update mode is selected (iue = 1 ), and the pwm duty cycle is provided via the master duty cycle (mdc) register (mdcs = 1 mode), the updates to the mdc register are synchronized to the pwm time base instead of an immediate update (duty cycle will be updated on the next pwm period). work arounds work around 1: use the enable immediate period update mode (eipu = 1 ) in conjunction with pwm immediate update mode (iue = 1 ). this will update the period and duty cycle on an immediate basis. work around 2: use individual duty cycle registers (pdcx) and pwm immediate update mode (iue = 1 ) to update individual duty cycle registers on an immediate basis. affected silicon revisions 3. module: pwm if pwm fault interrupts are disabled (fltien = 0 or clien = 0 ), then associated status bits (fltstat and clstat) will not function. work around enable pwm fault interrupts (fltien = 1 , clien = 1 ). affected silicon revisions 4. module: pwm the pwm output will exhibit jitter under the following conditions: when the pwm clock divider has the value of 1, 5 or 6 (ptcon2 = 0b001 , 0b101 or 0b110 ), and the three least significant bits of the pwm period register (ptper or phasex), duty cycle register (mdc or pdcx) or phase register (phasex) are non-zero. work around use pwm clock dividers other than 1, 5 or 6. affected silicon revisions note: this document summarizes all silicon errata issues from all revisions of silicon, previous as well as current. only the issues indicated by the shaded column in the following tables apply to the current silicon revision ( a4 ). a2 a3 a4 xx x a2 a3 a4 xx x a2 a3 a4 xx x a2 a3 a4 xx x
dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 ds80439m-page 6 ? 2009-2013 microchip technology inc. 5. module: pwm when pwm module is operated in complementary, redundant and push-pull output modes, with independent time base (itb = 1 ) and independent fault mode (ifltmod = 1 ) enabled, the pwmxh and pwmxl outputs should be affected by the fault and current-limit events as follows: ? pwmxh is affected by current-limit source (fclcon) and the current-limit should be reset at the end of the primary local time base. ? pwmxl is affected by fault source (fclcon) and the fault should be reset at the end of the primary local time base. on silicon revisions affected by this erratum, the current-limit event works correctly for the pwmxh pin. however, the fault event is reset by the secondary local time base although it is not used to generate the time base value. as a result, the fault event on pwmxl pin may not work as expected. this erratum only applies to the cycle-by-cycle fault mode (fltmod = 0b01). work around if pwm is in complementary, redundant or push- pull mode and (itb = 1 ), set sphasex to have the same value as phasex. this will ensure that the fault event on the pwmxl pin is reset at the start of the new pwm period for cycle-by-cycle independent fault operation. affected silicon revisions 6. module: pwm the independent time base pwm outputs may not be synchronized with the master time base pwm outputs when both modes are used simultaneously. work around to synchronize the independent pwm outputs with the master time base pwm outputs, disable the immediate update enable bit (iue = 0 ), ensure that the three least significant bits of the period are zero, and that the duty cycle is between 8 ns and the period minus 0x8. this work around will not work if the frequency of the pwm module is being updated on the fly. affected silicon revisions 7. module: pwm in pwm latched fault mode, the pwm outputs may be latched on both the rising as well as the falling edge of the fault signal, regardless of the fault input polarity selection (set with the fclconx bit setting). work around none. affected silicon revisions 8. module: pwm a bit write to the clmod bit (bit 8) in the fclconx register or consecutive writes to the lower byte and higher byte of the fclconx register, causes all other bits of the high byte to be loaded with zeros. work around use word writes for the fclconx register instead of bit or byte writes. affected silicon revisions a2 a3 a4 xx x a2 a3 a4 xx x a2 a3 a4 xx x a2 a3 a4 xx x
? 2009-2013 microchip technology inc. ds80439m-page 7 dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 9. module: pwm the pwm module fails to wake the cpu from sleep mode on a pwm fault event. work around use the external interrupt pins to wake the cpu from sleep mode. affected silicon revisions 10. module: comparator if the slew rate of the comparator input signal is lower than 198 mv/s, the comparator module generates erroneous triggers/interrupts. work around the slew rate of comparator input signal must be higher than 198 mv/s to avoid multiple triggers/ interrupts. affected silicon revisions 11. module: adc selecting the primary frc (f vco ) as a clock source for the adc module by setting the slowclk bit (adcon<12>) to the default setting of ? 0 ?, does not work. work around always set the slowclk bit (adcon<12>) to ? 1 ?, which selects the auxiliary clock (aclk) as a clock source for the adc. use the auxiliary clock configuration registers to select the primary frc (f vco ) as a source (if desired) or other clock sources as inputs. see section 8.0 ?oscillator configuration? of the device data sheet (ds70318) for more information. affected silicon revisions 12. module: auxiliary clock when the pwmmd bit in the pmd1 register is set, the auxiliary clock to both the adc and pwm modules is disabled. work around to disable the auxiliary clock for the pwm module but not for the adc module, set the individual pwm generator pmd bits in the pmd6 register. affected silicon revisions 13. module: comparator the comparator interrupt should be generated on a rising edge of the comparator output. when using the inverted polarity setting for the analog comparator (cmpconx = 1 ), the interrupt should be generated when the analog voltage at the comparator input falls below the programmable threshold determined by the cmpdac register setting. however, with this setting the interrupts may be generated regardless of the state of the comparator. work around when using comparator interrupts, configure the external circuit to use the non-inverted polarity comparator setting (cmpconx = 0 ). affected silicon revisions 14. module: uart when the uart is in 4x mode (brgh = 1 ) and using two stop bits (stsel = 1 ), it may sample the first stop bit instead of the second one. this issue does not affect the other uart configurations. work around use the 16x baud rate option (brgh = 0 ) and adjust the baud rate accordingly. affected silicon revisions a2 a3 a4 xx x a2 a3 a4 xx x a2 a3 a4 xx x a2 a3 a4 xx x a2 a3 a4 xx x a2 a3 a4 xx x
dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 ds80439m-page 8 ? 2009-2013 microchip technology inc. 15. module: uart when the uart is configured for ir interface operations (uxmode<9:8> = 11 ), the 16x baud clock signal on the bclk pin is present only when the module is transmitting. the pin is idle at all other times. work around configure one of the output compare modules to generate the required baud clock signal when the uart is receiving data or in an idle state. affected silicon revisions 16. module: i 2 c? if there are two i 2 c devices on the bus, one of them is acting as the master receiver and the other as the slave transmitter. if both devices are configured for 10-bit addressing mode, and have the same value in the a10 and a9 bits of their addresses, then when the slave select address is sent from the master, both the master and slave acknowledge it. when the master sends out the read operation, both the master and the slave enter into read mode and both of them transmit the data. the resultant data will be the anding of the two transmissions. work around in all i 2 c devices, the addresses as well as bits a10 and a9 should be different. affected silicon revisions 17. module: pwm when the primary or secondary pwmx generator is selected as a trigger source for adc convert pairs 3, 4, 5 or 6 and the pwm module is running at the maximum speed, the pwm module may fail to trigger a conversion on these adc pairs. work arounds work around 1: configure the pwm module to trigger the adc module per the following steps (see example 1 for the code used in this work around): 1. enable the dual trigger mode bit (dtm) in the trgconx register. 2. configure the trigx register to the desired trigger point. 3. configure the strigx register to trigx + 0x8. 4. select the pwmx primary trigger as the adc trigger source for conversion. if the pwm channel is configured for independent output mode and both channels are operating on the same time base, the phase difference between the two channels must be considered when setting the strigx register. this work around will not work for true independent time base mode. with this work around, the pwmx secondary trigger should not be selected as the trigger source for the adc convert pair. work around 2: configure the pwm input clock prescaler bits (pclkdiv) for divide by 2 or higher. work around 3: utilize other available trigger sources, such as software or timer triggers, to initiate conversion on the affected adc convert pairs. affected silicon revisions example 1: using dual trigger mode a2 a3 a4 xx x a2 a3 a4 xx x a2 a3 a4 x trgcon1bits.dtm = 1; /* dual trigger mode (dtm) and strig used in combination to generate */ /* adcpx triggers */ trig1 = 1224; /* configure desired trigger */ strig1 = 1232; /* strig1 should be configured for trig1 + 8 */ adcpc2bits.trgsrc5 = 0x4; /* pwm1 primary trigger selected as adc trigger source for adcp5*/
? 2009-2013 microchip technology inc. ds80439m-page 9 dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 18. module: pgec3/pged3 programming pins when using the pgec3/pged3 pins for device programming, the programming time may be slower as compared to other available pgecx/ pgedx pin pairs, because the enhanced icsp? programming algorithm cannot be executed on this pin pair. refer to the ?dspic33f/pic24h flash programming specification? (ds70152) for additional information on this limitation. work around use alternate pgecx/pgedx programming pin pairs. affected silicon revisions 19. module: uart the uart module will not generate consecutive break characters. trying to perform a back-to- back break character transmission will cause the uart module to transmit the dummy character used to generate the first break character instead of transmitting the second break character. break characters are generated correctly if they are followed by non-break character transmission. work around none. affected silicon revisions 20. module: pwm cycle-by-cycle current-limit operation does not work when the pwm module is configured for center-aligned mode. work around none. affected silicon revisions 21. module: pwm during normal operation, if leading-edge blanking (leb) is triggered to start counting at a rising edge of pwm and the pwm module has a blanking time period less than the pwm assertive time (t on time), and the current-limit event occurs during the t on period and is still pending after the t on period is over, the current-limit event should be ignored during t on time, but should be recognized after the t on time is over. however, the device fails to recognize the current- limit event after t on time is over, when previously described conditions exist. work around initialize the lebconx register as shown below, which specifies the leb function for the (clsrc) input to be triggered on the falling (trailing) edge of pwm, and set the leb delay to a minimum value of 8 ns: ? phf bit is set ? clleben bit is set ? leb<9:3> bits are set to a minimum value of ? 1 ? if the user application needs leb to be triggered at a falling edge, make sure that the leb delay is set for more than the t on time. affected silicon revisions 22. module: uart when the uart is operating in 8-bit mode (pdsel = 0x) and using the irda ? encoder/ decoder (iren = 1 ), the module incorrectly transmits a data payload of 80h as 00h. work around none. affected silicon revisions a2 a3 a4 xx x a2 a3 a4 xx x a2 a3 a4 xx x a2 a3 a4 xx x a2 a3 a4 xx x
dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 ds80439m-page 10 ? 2009-2013 microchip technology inc. 23. module: uart the uart error interrupt may not occur, or may occur at an incorrect time, if multiple errors occur during a short period of time. work around read the error flags in the uxsta register whenever a byte is received to verify the error status. in most cases, these bits will be correct, even if the uart error interrupt fails to occur. affected silicon revisions 24. module: i 2 c when the i 2 c module is configured as a 10-bit slave with an address of 0x102, the i2cxrcv register content for the lower address byte is 0x01 rather than 0x02; however, the module acknowledges both address bytes. work around none. affected silicon revisions 25. module: i 2 c in 10-bit addressing mode, some address matches do not set the rbf flag or load the receive register i2cxrcv, if the lower address byte matches the reserved addresses. in particular, these include all addresses with the form xx0000xxxx and xx1111xxxx, with the following exceptions: ? 001111000x ? 011111001x ? 101111010x ? 111111011x work around ensure that the lower address byte in 10-bit addressing mode does not match any 7-bit reserved addresses. affected silicon revisions 26. module: psv operations an address error trap occurs in certain addressing modes when accessing the first four bytes of an psv page. this occurs only when using the following addressing modes: ? mov.d ? register indirect addressing (word or byte mode) with pre/post-decrement work around do not perform psv accesses to any of the first four bytes using the above addressing modes. for applications using the c language, mplab c30 version 3.11 or higher, provides the following command-line switch that implements a work around for the erratum. -merrata=psv_trap refer to the readme.txt file in the mplab c30 v3.11 toolsuite for further details. affected silicon revisions 27. module: comparator the comparator fails to wake the cpu from sleep mode when the internal voltage reference is used (i.e., the extref bit is set to ? 0 ?). work around use the external reference source by setting the extref bit to ? 1 ?. affected silicon revisions 28. module: pwm when multiple pwm channels are operating in independent time base mode (itb = 1 ) and the frequency is being updated on the fly, pwm channels configured for push-pull mode may not remain synchronized with other pwm output modes. work around when multiple pwm channels are operating in independent time base mode, immediate updates to the pwm module (iue = 1 ) must be enabled for pwm channels to remain synchronized. affected silicon revisions a2 a3 a4 xx x a2 a3 a4 xx x a2 a3 a4 xx x a2 a3 a4 xx x a2 a3 a4 xx x a2 a3 a4 xx x
? 2009-2013 microchip technology inc. ds80439m-page 11 dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 29. module: analog comparator the internal band gap reference voltage (intref) for the analog comparator provides the reference to the analog comparator if the extref bit (cmpconx<5>) = 0 and the range bit (cmpconx<0>) = 0 .the data sheet states that the intref voltage should be 1.2v nominal and within 1%. however, the internal band gap reference voltage does not meet the specification stated above. for the actual range of the intref voltage, refer to the iv ref specification in the ?electrical characteristics? chapter of the device data sheet. work arounds to avoid this issue, implement one of the following two work arounds, depending on the application requirements. work around 1: use an external voltage reference for the analog comparator by setting the extref bit (cmpconx<5>) = 1 and providing an external reference to the extref pin. work around 2: use the high-range setting for the internal reference by setting the extref bit (cmpconx<5>) = 0 and the range bit (cmpconx<0>) = 1 . this setting uses av dd /2 as the comparator reference voltage. affected silicon revisions 30. module: auxiliary pll for extended temperature devices (designated with the -e suffix in the device part number) with the date code of 09xx, the auxiliary pll input frequency does not meet the published specification range at operating temperatures above 85oc. work around use the internal frc oscillator as the input to the auxiliary pll, or use the external oscillator with a frequency of 7.37 mhz. affected silicon revisions a2 a3 a4 xx x a2 a3 a4 xx x
dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 ds80439m-page 12 ? 2009-2013 microchip technology inc. 31. module: adc if the adc module is in an enabled state when the device enters sleep mode as a result of executing a pwrsav #0 instruction, the device power-down current (i pd ) may exceed the specifications listed in the device data sheet. this may happen even if the adc module is disabled by clearing the adon bit prior to entering sleep mode. work arounds work around 1: in order to remain within the i pd specifications listed in the device data sheet, the user software must completely disable the adc module by setting the adc module disable bit in the corresponding peripheral module disable register (pmdx), prior to executing a pwrsav #0 instruction. work around 2: if the adc module was previously initialized and enabled, before entering sleep, execute the lines of code provided in example 2 . example 2: affected silicon revisions note: the adc module must be reinitialized by the user application before resuming adc operation. note: unlike work around 1 , the user application does not need to reinitialize the adc module; however, it is necessary to re-enable the adc module by setting the adon bit after waking from sleep. ad1con1bits.adon = 0; //disable the adc module __asm__ volatile ("repeat #50"); //wait 50 t cy __asm__ volatile ("nop"); //repeat nop 51 times sleep(); // execute pwrsav #0 and go to sleep a2 a3 a4 xx x
? 2009-2013 microchip technology inc. ds80439m-page 13 dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 32. module: high-speed pwm the penh and penl bits in the ioconx register are used to assign ownership of the pins to either the pwm module or the gpio module. the correct procedure to configure the pwm module is to assign pin ownership to the pwm module and then enabling it using the pten bit in the ptcon register. if the pwm module is enabled using the above sequence, then a glitch may be observed on the pwm pins before actual switching of the pwm outputs begins. this glitch may cause momentary turn-on of power mosfets that are driven by the pwm pins and may cause damage to the application hardware. work around follow the given sequence to avoid any glitches from appearing on the pwm outputs at the time of enabling. 1. configure the respective pwm pins to digital inputs using the trisx registers. this step will put the pwm pins in a high-impedance state. the pwm outputs must be maintained in a safe state by using pull-up or pull-down resistors. 2. assign pin ownership to the gpio module by configuring ioconx = 0 and ioconx = 0 . 3. specify the pwm override state to the desired safe state for the pwm pins using the ovrdat<1:0> bit field in the ioconx register. 4. override the pwm outputs by setting ioconx = 1 and ioconx = 1 . 5. enable the pwm module by setting ptcon = 1 . 6. remove the pwm overrides by making ioconx = 0 and ioconx = 0 . 7. ensure a delay of at least one full pwm cycle. 8. assign pin ownership to the pwm module by setting ioconx = 1 and ioconx = 1 . the code in example 3 illustrates the use of this work around. affected silicon revisions example 3: configure pwm module to prevent glitches on pwm1h and pwm1l pins at the time of enabling a2 a3 a4 xx x trisabits.trisa4 = 1; // configure pwm1h/ra4 as digital input // ensure output is in safe state using pull-up or // pull-down resistors trisabits.trisa3 = 1; // configure pwm1l/ra3 as digital input // ensure output is in safe state using pull-up or // pull-down resistors iocon1bits.penh = 0; // assign pin ownership of pwm1h/ra4 to gpio module iocon1bits.penl = 0; // assign pin ownership of pwm1l/ra3 to gpio module iocon1bits.ovrdat = 0; // configure override state of the pwm outputs to // desired safe state. iocon1bits.ovrenh = 1; // override pwm1h output iocon1bits.ovrenl = 1; // override pwm1l output ptconbits.pten = 1; // enable pwm module iocon1bits.ovrenh = 0; // remove override for pwm1h output iocon1bits.ovrenl = 0; // remove override for pwm1l output delay(x); // introduce a delay greater than one full pwm cycle iocon1bits.penh = 1; // assign pin ownership of pwm1h/ra4 to pwm module iocon1bits.penl = 1; // assign pin ownership of pwm1l/ra3 to pwm module
dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 ds80439m-page 14 ? 2009-2013 microchip technology inc. 33. module: reserved the issue in a previous version of the document was removed. 34. module: pwm the high-speed pwm provides a feature to update the pwm duty cycle at any time during the pwm period. the new duty cycle should take effect: ? on the next pwm period when immediate duty cycle updates are disabled (pwmconx = 0 ). ? on the same pwm period when immediate duty cycle updates are enabled (pwmconx = 1 ). however, when the immediate duty cycle updates are disabled and the duty cycle update coincides with a pwm period roll-over, the pwm output may be corrupted and exhibit a 100% duty cycle for one pwm period. the new duty cycle value will take effect on the next pwm period. work around enable immediate duty cycle updates by configuring pwmconx = 1 . affected silicon revisions 35. module: jtag in jtag mode, the tms pin will not have an active pull-up as required by the jtag specification. instead, the pull-up function will be enabled on the tck pin. work around an external pull-up resistor can be connected to the tms pin to ensure that the signal does not enter a tri-state condition when in jtag mode. there is no work around for the wrongly enabled pull-up function on the tck pin. affected silicon revisions 36. module: spi when the spi module is configured in framed master mode and the frame sync pulse edge select bit (frmdly) is set to ? 1 ?, transmitting a word and then buffering another word in the spix- buf register before the transmission has com- pleted, results in an incomplete transmission of the first data word. only the first 15 bits from the first data word are transmitted, followed by the sync pulse and the complete second word. work around between the two back-to-back spi operations, add a delay to ensure that the first word is fully transmitted before the second word is written to the spixbuf register, as shown in example 4 . example 4: affected silicon revisions 37. module: comparator with the dac output is disabled by clearing the dacoen bit (cmpconx<8>), output signal transitions occurring on the dacout pin can cause the comparator trigger voltage level to change. for example, if the uart1 transmit (u1tx) signal is mapped to the same pin as dacout, uart data transmissions can cause the comparator to get triggered at different trigger levels than what is programmed through the cmpdacx register. work around when the comparator is enabled, do not use the dacout pin, either as a general purpose i/o pin or a peripheral output signal. affected silicon revisions a2 a3 a4 xx x note: this issue is only present in the dspic33fj06gs101 device. a2 a3 a4 xx x a2 a3 a4 xx x a2 a3 a4 xx x spi1buf = 0x0001; while (spi1statbits.spitbf); asm("repeat #50");. asm("nop"); // the number of nops depends on the spi // clock prescalers spi1buf = 0x0002;
? 2009-2013 microchip technology inc. ds80439m-page 15 dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 38. module: cpu when a previous disi instruction is active (i.e., the disicnt register is non-zero), and the value of the disicnt register is updated manually, the disicnt register freezes and disables interrupts permanently. work around avoid updating the disicnt register manually. instead, use the disi #n instruction with the required value for ? n ?. affected silicon revisions 39. module: cpu when using the signed 32-by-16-bit division instruction, div.sd , the overflow bit does not always get set when an overflow occurs. work around test for and handle overflow conditions outside of the div.sd instruction. affected silicon revisions 40. module: uart when using utxisel = 01 (interrupt when last character is shifted out of the transmit shift register) and the final character is being shifted out through the transmit shift register, the transmit (tx) interrupt may occur before the final bit is shifted out. work around if it is critical that the interrupt processing occur only when all transmit operations are complete. hold off the interrupt routine processing by adding a loop at the beginning of the routine that polls the transmit shift register empty bit (trmt) before processing the rest of the interrupt. affected silicon revisions 41. module: jtag jtag flash programming is not supported. work around none. affected silicon revisions 42. module: pwm when operating in edge-aligned complimentary mode, if the duty cycle (pdcx) becomes less than the alternate dead time (altdtrx), the dead time on the pwms will become 0. work around ensure that the duty cycle (pdcx) always meets the following condition: pdcx > (altdtrx ? 1). affected silicon revisions 43. module: pwm if the pwm clock divider select register, ptcon2, is not equal to zero, the pwm module may or may not initialize from an override state (ioconxbits.ovrenh = 1 or ioconxbits.ovrenl = 1 ). work around when configuring the override enable bits (ovrenl/ovrenh) in the pwmx i/o control register, ioconx, set these bits implicitly via word format and not explicitly via bit format. for example: ioconx = ioconx & 0xfcff; affected silicon revisions a2 a3 a4 xx x a2 a3 a4 xx x a2 a3 a4 xx x a2 a3 a4 xx x a2 a3 a4 xx x a2 a3 a4 xx x
dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 ds80439m-page 16 ? 2009-2013 microchip technology inc. 44. module: pwm if the pwm is configured for complimentary mode and the swap bit is enabled, the pwm outputs might operate as redundant mode when the phase value is greater than the programmed dead-time (dtrx) value. work around using true independent output mode with the independent time base mode bit (itb) set to ? 0 ?, the pwm module can be configured to replicate the original complementary signal by properly setting up the phase (phasex, spasex) and the independent duty cycle (pdcx, sdcx). affected silicon revisions 45. module: pwm the pwm current-limit operation allows the pwm module to set/reset the output signals when a specific current limit is detected with a minimum latency delay. when operating the pwm module in complementary mode (pmod = 0 ), positive dead time, and with current-limit interrupt enable (clien = 1 ), a less than 8-ns pulse glitch on the complementary output may be present right after the current limit is detected. this glitch, if present, will occur prior to the implementation of the dead time. work around in order to avoid the <8 ns glitch to be propagated into the mosfet gate driver, a low-pass filter (e.g., resistor-capacitor network) should be implemented between the dspic ? dsc pwm output pin and the gate driver ic input pin. affected silicon revisions a2 a3 a4 xx x a2 a3 a4 xx x
? 2009-2013 microchip technology inc. ds80439m-page 17 dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 data sheet clarifications the following typographic corrections and clarifications are to be noted for the latest version of the device data sheet (ds70318 f ): 1. module: idle current (i idle ) the typical values for table 24-6 were stated incorrectly in the data sheet. the correct values are shown in tab l e 3 . note: corrections are shown in bold . where possible, the original bold text formatting has been removed for clarity. table 3: dc characteristics: idle current (i idle ) dc characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial -40c ? t a ? +125c for extended param no. typical (1) max units conditions idle current (i idle ): core off clock on base current (2) dc40d 48 ?ma -40c 3.3v 10 mips ( 3) dc40a 48 ?ma +25c dc40b 48 ?ma +85c dc40c 48 ? ma +125c dc41d 60 ?ma -40c 3.3v 16 mips (3) dc41a 60 ma +25c ? dc41b 60 ?ma +85c dc41c 60 ? ma +125c dc42d 68 ?ma -40c 3.3v 20 mips (3) dc42a 68 ?ma +25c dc42b 68 ?ma +85c dc42c 68 ? ma +125c dc43d 77 ?ma -40c 3.3v 30 mips (3) dc43a 77 ?ma +25c dc43b 77 ?ma +85c dc43c 77 ? ma +125c dc44d 86 ?ma -40c 3.3v 40 mips dc44a 86 ?ma +25c dc44b 86 ?ma +85c dc44c 86 ? ma +125c note 1: data in ?typical? column is at 3.3v, +25c unless otherwise stated. 2: base i idle current is measured with core off, clock on and all modules turned off. peripheral module disable sfr registers are zeroed. all i/o pins are configured as inputs and pulled to v ss . 3: these parameters are characterized but not tested in manufacturing.
dspic33fj06gs101/x02 and dspic33fj16gsx02/x04 ds80439m-page 18 ? 2009-2013 microchip technology inc. appendix a: revision history rev a document (3/2009) initial release of this document; issued for revision a2 silicon. includes silicon issues 1-9 ( pwm ), 10 ( comparator ), 11 ( adc ), 12 ( auxiliary clock ), 13 ( comparator ), 14-15 ( uart ) and 16 ( i 2 c? ). rev b document (4/2009) added silicon issue 17 ( pwm ). rev c document (5/2009) updated silicon issue 17 ( pwm ) to clarify which adc pairs are involved. rev d document (5/2009) revised to include revision a3 silicon information. added silicon issues 18 ( pgec3/pged3 programming pins ), 19 ( uart ) and 20-21 ( pwm ). added data sheet clarification 1 ( idle current (i idle ) ). rev e document (8/2009) added silicon issues 22-23 ( uart ), 24-25 ( i 2 c ), 26 ( psv operations ), 27 ( comparator ) and 28 ( pwm ). rev f document (1/2010) added silicon issues 29 ( analog comparator ) and 30 ( auxiliary pll ). added data sheet clarification 2 ( auxiliary pll ). rev g document (6/2010) added silicon issues 31 ( adc ) and 32 ( high-speed pwm ) and data sheet clarification 3 ( dc characteristics: i/o pin input specifications ). rev h document (10/2010) added revision a4 silicon information to all tables. updated the work arounds for silicon issue 31 ( adc ). removed silicon issue 33 (pwm) and marked its location as reserved. added silicon issues 34 ( pwm ) and 35 ( jtag ). rev j document (3/2011) updated silicon issue 29 ( analog comparator ). added silicon issues 36 ( spi ) and 37 ( comparator ). added data sheet clarification 4 (). rev k document (11/2011) added silicon issues 38 ( cpu ), 39 ( cpu ), 40 ( uart ), 41 ( jtag ), and 42 ( pwm ). rev l document ( 5 /2012 ) removed data sheet clarifications 2, 3, and 4. updated silicon issues 29 ( analog comparator ) and 32 ( high-speed pwm ). added silicon issues 43 ( pwm ) and 44 ( pwm ). rev m document (1 / 201 3) ammends silicon issue 43 with correct pwm clock divider select register bit name (changed from ptcon to ptcon2). includes silicon issue 45 ( pwm ).
? 2009-2013 microchip technology inc. ds80439m-page 19 information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. it is your responsibility to ensure that your application meets with your specifications. microchip makes no representations or warranties of any kind whether express or implied, written or oral, statutory or otherwise, related to the information, including but not limited to its condition, quality, performance, merchantability or fitness for purpose . microchip disclaims all liability arising from this information and its use. use of microchip devices in life support and/or safety applications is entirely at the buyer?s risk, and the buyer agrees to defend, indemnify and hold harmless microchip from any and all damages, claims, suits, or expenses resulting from such use. no licenses are conveyed, implicitly or otherwise, under any microchip intellectual property rights. trademarks the microchip name and logo, the microchip logo, dspic, flashflex, k ee l oq , k ee l oq logo, mplab, pic, picmicro, picstart, pic 32 logo, rfpic, sst, sst logo, superflash and uni/o are registered trademarks of microchip technology incorporated in the u.s.a. and other countries. filterlab, hampshire, hi-tech c, linear active thermistor, mtp, seeval and the embedded control solutions company are registered trademarks of microchip technology incorporated in the u.s.a. silicon storage technology is a registered trademark of microchip technology inc. in other countries. analog-for-the-digital age, app lication maestro, bodycom, chipkit, chipkit logo, codeguard, dspicdem, dspicdem.net, dspicworks, dsspeak, ecan, economonitor, fansense, hi-tide, in-circuit serial programming, icsp, mindi, miwi, mpasm, mpf, mplab certified logo, mplib, mplink, mtouch, omniscient code generation, picc, picc-18, picdem, picdem.net, pickit, pictail, real ice, rflab, select mode, sqi, serial quad i/o, total endurance, tsharc, uniwindriver, wiperlock, zena and z-scale are trademarks of microchip technology incorporated in the u.s.a. and other countries. sqtp is a service mark of microchip technology incorporated in the u.s.a. gestic and ulpp are registered trademarks of microchip technology germany ii gmbh & co. & kg, a subsidiary of microchip technology inc., in other countries. all other trademarks mentioned herein are property of their respective companies. ? 2009-2013, microchip technology incorporated, printed in the u.s.a., all rights reserved. printed on recycled paper. isbn: 978-1-62076-873-0 note the following details of the code protection feature on microchip devices: ? microchip products meet the specification contai ned in their particular microchip data sheet. ? microchip believes that its family of products is one of the most secure families of its kind on the market today, when used i n the intended manner and under normal conditions. ? there are dishonest and possibly illegal methods used to breach the code protection feature. all of these methods, to our knowledge, require using the microchip produc ts in a manner outside the operating specif ications contained in microchip?s data sheets. most likely, the person doing so is engaged in theft of intellectual property. ? microchip is willing to work with the customer who is concerned about the integrity of their code. ? neither microchip nor any other semiconduc tor manufacturer can guarantee the security of their code. code protection does not mean that we are guaranteeing the product as ?unbreakable.? code protection is constantly evolving. we at microchip are co mmitted to continuously improvin g the code protection features of our products. attempts to break microchip?s code protection feature may be a violation of the digital millennium copyright act. if such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that act. microchip received iso/ts-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in chandler and tempe, arizona; gresham, oregon and design centers in california and india. the company?s quality system processes and procedures are for its pic ? mcus and dspic ? dscs, k ee l oq ? code hopping devices, serial eeproms, microperipherals, nonvolatile memory and analog products. in addition, microchip?s quality system for the design and manufacture of development systems is iso 9001:2000 certified. quality management s ystem certified by dnv == iso/ts 16949 ==
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